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Integrated Circuit Systems, Inc.
ICS8431-11
255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER
FEATURES
* Fully integrated PLL * Differential 3.3V LVPECL output * Programmable PLL loop divider for generating a variety of output frequencies. * Crystal oscillator interface * Spread Spectrum Clocking (SSC) fixed at 1/2% modulation for environments requiring ultra low EMI * Typical RMS cycle-to-cycle jitter 2.6 ps * LVTTL / LVCMOS control inputs * PLL bypass modes supporting in-circuit testing and on-chip functional block characterization * 3.3V supply voltage * 28 lead SOIC * 0C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS8431-11 is a general purpose clock frequency synthesizer for IA64/32 application and HiPerClockSTM a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The VCO operates at a frequency range of 190MHz to 510MHz providing an output frequency range of 95MHz to 255MHz. The output frequency can be programmed using the parallel interface, M0 thru M8, to the configuration logic. Spread spectrum clocking is programmed via the control inputs SSC_CTL0 and SSC_CTL1.
,&6
Programmable features of the ICS8431-11 support four operational modes. The four modes are spread spectrum clocking (SSC), non-spread spectrum clock and two test modes which are controlled by the SSC_CTL[1:0] pins. Unlike other synthesizers, the ICS8431-11 can immediately change spread-spectrum operation without having to reset the device. In SSC mode, the output clock is modulated in order to achieve a reduction in EMI. In one of the PLL bypass test modes, the PLL is disconnected as the source to the differential output allowing an external source to be connnected to the TEST_I/O pin. This is useful for incircuit testing and allows the differential output to be driven at a lower frequency throughout the system clock tree. In the other PLL bypass mode, the oscillator divider is used as the source to both the M and the Fout divide by 2. This is useful for characterizing the oscillator and internal dividers.
BLOCK DIAGRAM
XTAL1 OSC XTAL2 / 16
PIN ASSIGNMENT
M0 M1 M2 M3 M4 M5 M6 M7 M8 SSC_CTL0 SSC_CTL1 VEE TEST_I/O VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 nP_LOAD VDDI XTAL2 XTAL1 nc nc VDDA VEE MR nc VDDO FOUT nFOUT VEE
PHASE DETECTOR
PLL
VCO /M
/2
FOUT nFOUT
ICS8431-11
TEST_I/O M0:M8 Configuration Logic SSC Control Logic
28-Lead SOIC M Package Top View
nP_LOAD
ICS8431CM-11
SSC_CTL0 SSC_CTL1
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REV. A JULY 11, 2001
Integrated Circuit Systems, Inc.
ICS8431-11
255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER
Type Input Input Input Power Input / Output Power Power Output Power Unused Input Power Power Input Power Input Pulldown Pullup Pullup Description M divider inputs. Data latched on LOW-to-HIGH transistion of nP_LOAD input. LVCMOS / LVTTL pins interface levels. M divider inputs. Data latched on LOW-to-HIGH transistion of nP_LOAD input. LVCMOS / LVTTL pins interface levels. SCC control pins. LVTTL / LVCMOS interface levels. Ground pin for core and test output. Programmed as input in PLL bypass mode. Power supply pin for core and test output. Ground pin for output. These differential outputs are main output drivers for the synthesizer. They are compatible with terminated positive referenced LVPECL logic. Power supply pin for output. No connection. Pulldown Reset M counter. Forces FOUT low. Ground pin. PLL power supply pin. Cr ystal oscillator input. Power supply pin for core. Pulldown M divider latch enable input. LVTTL / LVCMOS interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1-5 6-8 10, 11 12 13 14 15 16, 17 18 19, 23, 24 20 21 22 25, 26 27 28 Name M0-M6 M7-M8 SSC CTL0, SSC CTL1 VEE TEST I/O VDD VEE nFOUT, FOUT VDDO nc MR VEE VDDA XTAL1, XTAL2 VDDI nP_LOAD
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Pin Capacitance Input Pullup Resistor Input Pulldown Resistor 51 51 Test Conditions Minimum Typical Maximum 4 Units pF K K
ICS8431CM-11
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REV. A JULY 11, 2001
Integrated Circuit Systems, Inc.
ICS8431-11
255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. SSC CONTROL INPUT FUNCTION TABLE
Outputs Operational Modes FOUT, SSC_CTL1 SSC_CTL0 TEST_I/O nFOUT fXTAL / 16 PLL bypass; Oscillator, oscillator, M and N 0 0 Internal Disabled fXTAL / 32 /M dividers test mode. NOTE 1 fXTAL x M 0 1 PLL Enabled Hi-Z Default SSC; Modulation Factor = 1/2 Percent 32 PLL Bypass Mode, 1 0 External Disabled Test Clk Input (1MHz Test Clk 200MHz); NOTE 1 fXTAL x M 1 1 PLL Disabled Hi-Z No SSC Modulation 32 NOTE 1: Used for in house debug and characterization. TEST_I/O Source SSC Inputs
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
VCO Frequency (MHz) 190 191 192 193 * * 508 509 510 M Count 190 191 192 193 * * 508 509 510 256 M8 0 0 0 0 * * 1 1 1 128 M7 1 1 1 1 * * 1 1 1 64 M6 0 0 1 1 * * 1 1 1 32 M5 1 1 0 0 * * 1 1 1 16 M4 1 1 0 0 * * 1 1 1 8 M3 1 1 0 0 * * 1 1 1 4 M2 1 1 0 0 * * 1 1 1 2 M1 1 1 0 0 * * 0 0 1 1 M0 0 1 0 1 * * 0 1 0
NOTE 1: Assumes a 16MHz crystal.
ICS8431CM-11
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REV. A JULY 11, 2001
Integrated Circuit Systems, Inc.
ICS8431-11
255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V 0C to 85C -65C to 150C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Inputs Outputs Ambient Operating Temperature Storage Temperature
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of product at these condition or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDI = VDDO = 3.3V5%, TA = 0C TO 85C
Symbol VDD VDDO VDDA VDDI IEE Parameter Power Supply Voltage Output Power Supply Voltage Analog Power Supply Voltage Input Power Supply Voltage Test Conditions Minimum 3.135 3.135 3.135 3.135 Typical 3.3 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 3.465 140 Units V V V V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDI = VDDO = 3.3V5%, TA = 0C TO 85C
Symbol VIH Parameter M0:M8, SSC_CTL0, Input High Voltage SSC_CTL1, MR, TEST_I/O, nP_LOAD M0:M8, SSC_CTL0, Input Low Voltage SSC_CTL1, MR, TEST_I/O, nP_LOAD M7, M8, SSC_CTL0, SSC_CTL1, TEST_IO Input High Current M0:M6, nP_LOAD, MR M7, M8, SSC_CTL0, SSC_CTL1, TEST_IO Input Low Current M0:M6, nP_LOAD, MR Test Conditions 3.135V VDD 3.465V 3.135V VDD 3.465V VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 -5 Minimum 2 Typical Maximum VDD + 0.3 Units V
VIL
-0.3
0.8 5 150
V A A A A
IIH
IIL
TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = VDDA = VDDI = VDDO = 3.3V5%, TA = 0C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VDDO - 1.28 VDDO - 2.0 600 700 Typical Maximum VDDO - 0.98 VDDO - 1.7 850 Units V V mV
NOTE 1: Output terminated with 50 to VDDO - 2V.
ICS8431CM-11
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REV. A JULY 11, 2001
Integrated Circuit Systems, Inc.
ICS8431-11
255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum Typical 16.0 -50 -100 +50 +100 100 50 3 10 3 0 Per year @25C -5 18 7 32 7 70 +5 Maximum Units MHz ppm ppm W pF pF nH C ppm
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Frequency Tolerance Frequency Stability Drive Level Equivalent Series Resistance (ESR) Shunt Capacitance Load Capacitance Series Pin Inductance Operating Temperature Range Aging Fundamental
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDI = VDDO = 3.3V5%, TA = 0C TO 85C, 16MHZ CRYSTAL
Symbol Fave Parameter Average Output Frequency; NOTE 4 Cycle-to-Cycle Jitter ; NOTE 2 Output Duty Cycle; NOTE 2 Output Rise Time; NOTE 1, 2 Output Fall Time; NOTE 1, 2 Cr ystal Input Range; NOTE 3 SSC Modulation Frequency; NOTE 1, 2 SSC Modulation Factor ; NOTE 1, 2 Spectral Reduction; NOTE 1, 2 20% to 80% 20% to 80% FOUT = 200 MHz 47 300 300 14 30 0.4 7 10 10 450 450 16 Test Conditions Minimum -750 18 Typical Maximum +750 30 35 53 600 600 20 33.33 0.6 Units ppm ps ps % ps ps MHz KHz % dB ms
tj it(cc)
odc tR tF Fxtal Fm Fmf SSCred
tSTABLE Power-up to Stable Clock Output NOTE 1: Spread Spectrum clocking enabled. NOTE 2: Outputs terminated with 50 to VDDO - 2V. NOTE 3: Only valid within the VCO operating range. NOTE 4: Without external cr ystal components. tjit(cc), tR, tF, odc conform to JEDEC JESD65 definitions.
ICS8431CM-11
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REV. A JULY 11, 2001
Integrated Circuit Systems, Inc.
ICS8431-11
255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
80%
80%
Vswing 20% Clock Inputs and Outputs

20%
trise
AND
tfall
FIGURE 1 -- INPUT
OUTPUT SLEW RATES
FOUT
nFOUT
tcycle
n
tcycle
n+1
tjit(cc) = tcycle n -tcycle n+1
FIGURE 2 -- CYCLE-TO-CYCLE JITTER
nFOUT FOUT
Pulse Width (t
PW
) t
PERIOD
t odc = t
PW
PERIOD
FIGURE 3 -- odc & tPERIOD
ICS8431CM-11
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REV. A JULY 11, 2001
Integrated Circuit Systems, Inc.
FUNCTIONAL DESCRIPTION
ICS8431-11
255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER
The ICS8431-11 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A 16MHz series-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector. With a 16MHz crystal this provides a 1MHz reference frequency. The VCO of the PLL operates over a range of 190 to 510MHz. The output of the loop divider is also applied to the phase detector. The phase detector and the loop filter force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to the LVPECL output buffer. The divider provides a 50% output duty cycle. The programmable features of the ICS8431-11 support four output operational modes and a programmable PLL loop divider. The four output operational modes are spread spectrum clocking (SSC), non-spread spectrum clock and two test modes and are controlled by the SSC_CTL[1:0] pins. The PLL loop divider or M divider is programmed by using inputs M0 through M8. While the nP_LOAD input is held LOW, the data present at M0:M8 is transparent to the M-divider. On the LOW-to-HIGH transition of nP_LOAD, the M0:M8 data is latched into the M-divider and any further changes at the M0:M8 inputs will not be seen by the M-divider until the next LOW transition on nP_LOAD. The relationship between the VCO frequency, the crystal frequency and the loop counter/divider is defined as follows: fxtal x M 16 The M count and the required values of M0:M8 for programming the VCO are shown in Table 3B, Programmable VCO Frequency Function Table. The frequency out is defined as follows: fVCO = FOUT = fVCO = fxtal x M 2 32 For the ICS8431-11, the output divider equals 2. Valid M values for which the PLL will achieve lock are defined as 190 M 510.
ICS8431CM-11
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REV. A JULY 11, 2001
Integrated Circuit Systems, Inc.
ICS8431-11
255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER
CRYSTAL INPUT
AND
OSCILLATOR INTERFACE
The ICS8431-11 features an internal oscillator that uses an external quartz crystal as the source of its reference frequency. A 16MHz crystal divided by 16 before being sent to the phase detector provides the reference frequency. The oscillator is a series resonant, multi-vibrator type design. This design provides better stability and eliminates the need for large on chip capacitors. Though a series resonant crystal is preferred, a parallel resonant crystal can be used. A parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified. A few hundred ppm translates to KHz inaccuracy. In general computing applications this level of inaccuracy is irrelevant. If better ppm accuracy is required, an external capacitor can be added to a parallel resonant crystal in series to pin 25. Figure 1A shows how to interface with a crystal. Figures 1A, 1B, and 1C show various crystal parameters which are recommended only as guidelines. Figure 1A shows how to interface a capacitor with a parallel resonant crystal. Figure 1B shows the capacitor value needed for the optimum PPM performance over various parallel resonant crystals. Figure 1C shows the recommended tuning capacitance for a various parallel resonant crystal.
ICS8431-11
XTAL2
(Pin 26, SOIC)
XTAL1
FIGURE 1A. CRYSTAL INTERFACE
FIGURE 1B. Recommended tuning capacitance for various parallel resonant crystals.
FIGURE 1C. Recommended tuning capacitance for various parallel resonant crystal.
60 Series Capacitor, C1 (pF) 50 40 30 20
15.000 16.667 19.440 20.000 24.000
Frequency Accuracy (ppm)
14.318
10 0 14 15 16 17 18 19 20 21 22 23 24 25 Crystal Frequency (MHz)
100 80 60 40 20 0 -20 0 -40 -60 -80 -100
10
20
30
Optional
(Pin 25, SOIC)
40
50
60
19.44MHz
Series Capacitor, C1 (pF)
16MHz 15.00MHz
ICS8431CM-11
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REV. A JULY 11, 2001
Integrated Circuit Systems, Inc.
ICS8431-11
255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER
The ICS8431-11 triangle modulation frequency deviation will not exceed 0.6% down-spread from the nominal clock frequency (+0.0% / -0.5%). An example of the amount of down spread relative to the nominal clock frequency can be seen in the frequency domain, as shown in Figure 3. The ratio of this width to the fundamental frequency is typically 0.4%, and will not exceed 0.6%. The resulting spectral reduction will be greater than 7dB, as shown in Figure 3. It is important to note the ICS8431-11 7dB minimum spectral reduction is the component-specific EMI reduction, and will not necessarily be the same as the system EMI reduction.
SPREAD SPECTRUM
Spread-spectrum clocking is a frequency modulation technique for EMI reduction. When spread-spectrum is enabled, a 30KHz triangle waveform is used with 0.5% down-spread (+0.0% / -0.5%) from the nominal 200MHz clock frequency. An example of a triangle frequency modulation profile is shown in Figure 2 below. The ramp profile can be expressed as: * Fnom = Nominal Clock Frequency in Spread OFF mode (200MHz with 16MHz IN) * Fm = Nominal Modulation Frequency (30KHz) * = Modulation Factor (0.5% down spread) (1 - ) fnom + 2 fm x x fnom x t when 0 < t < 1, 2 fm (1 - ) fnom - 2 fm x x fnom x t when 1 < t < 1 2 fm fm
Fnom
- 10 dBm
B
A
(1 - ) Fnom
0.5/fm 1/fm
= .4%
FIGURE 3. 200MHZ CLOCK OUTPUT IN FREQUENCY DOMAIN FIGURE 2. TRIANGLE FREQUENCY MODULATION (A) SPREAD-SPECTRUM OFF (B) SPREAD-SPECTRUM ON
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8431-11 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDI, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, better power supply isolation is required. Figure 4 illustrates how a 10 along with a 10F and a .01F bypass capacitor should be connected to each power supply pin.
3.3V VDD .01F VDDA .01F 10 F 10
FIGURE 4. POWER SUPPLY FILTERING
ICS8431CM-11
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REV. A JULY 11, 2001
Integrated Circuit Systems, Inc.
ICS8431-11
255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER
drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. There are a few simple termination schemes. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V 5 2 Zo 5 2 Zo Zo = 50
TERMINATION
FOR
PECL OUTPUTS
The clock layout topology shown below is typical for IA64/32 platforms. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/PECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to
Zo = 50
Zo = 50
FOUT
FIN Zo = 50 Zo = 50 50 Zo = 50 FOUT 50 VCC-2V Zo = 50 3 2 Zo Zo = 50 3 2 Zo FIN
RTT =
1 (VOH + VOL / VCC -2) -2
Zo
FIGURE 5A. LVPECL OUTPUT TERMINATION
LAYOUT GUIDELINE
The schematic of the ICS8431-11 layout example used in this layout guideline is shown in Figure 6A. The ICS8431-11 recommended PCB board layout for this example is shown in Figure 6B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stacking of the P.C. board.
U1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 M0 M1 M2 M3 M4 M5 M6 M7 M8 SSC_CTL0 SSC_CTL1 GND TEST_IO VDD nP_LOAD VDDI XTAL1 XTAL2 NC NC VDDA NC NC NC VDDO FOUT nFOUT GND 28 27 26 25 24 23 22 21 20 19 18 17 16 15 C6 0.01uF VDD
VDD
8431-11 C1 0.1uF C2 0.1uF Zo = 50 Ohm INTL2 R2 84
ICS8431CM-11
RTT
FIGURE 5B. LVPECL OUTPUT TERMINATION
Termination A
X1 R5 VDDA 10 VDD C3 0.01uF C4 10uF R1 125 IN+ TL1 R3 125 VDD0
Termination B (not shown in the layout)
IN+ IN-
Zo = 50 Ohm
R2 50
R1 50
R4 84
R3 50
FIGURE 6A. RECOMMENDED SCHEMATIC LAYOUT www.icst.com/products/hiperclocks.html
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REV. A JULY 11, 2001
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The following component footprints are used in this layout example: All the resistors and capacitors are size 0603.
ICS8431-11
255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER
traces should be routed first and should be locked prior to routing other signals traces. * The traces with 50 transmission lines TL1 and TL2 at FOUT and nFOUT should have equal delay and run adjacent to each other. Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. * Keep the clock trace on same layer. Whenever possible, avoid any vias on the clock traces. Any via on the trace can affect the trace characteristic impedance and hence degrade signal quality. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow more space between the clock trace and the other signal trace. * Make sure no other signal trace is routed between the clock trace pair. The matching termination resistors R1, R2, R3 and R4 should be located as close to the receiver input pins as possible. Other termination scheme can also be used but is not shown in this example.
POWER
AND
GROUNDING
Place the decoupling capacitors C1, C2 and C3, C4, C5, C6 as close as possible to the power pins. If space allows, placing the decoupling capacitor at the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin generated by the via. Maximize the pad size of the power (ground) at the decoupling capacitor. Maximize the number of vias between power (ground) and the pads. This can reduce the inductance between the power (ground) plane and the component power (ground) pins. If VDDA shares the same power supply with VDD, insert the RC filter R5, C3, and C4 in between. Place this RC filter as close to the VDDA as possible.
CLOCK TRACES
AND
TERMINATION
The component placements, locations and orientations should be arranged to achieve the best clock signal quality. Poor clock signal quality can degrade the system performance or cause system failure. In the synchronous high-speed digital system, the clock signal is less tolerable to poor signal quality than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The trace shape and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal
CRYSTAL
The crystal X1 should be located as close as possible to the pins 26 (XTAL1) and 25 (XTAL2). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces.
U1 ICS8431-11 GND
C6
VDD X1 Signals VIA
C3 C4
R5
Close to the input pins of the receiver R1 R2 TL1 (50 Ohm) IN+
C2
C1
TL2 (50 Ohm)
INR3 R4
FIGURE 6B. PCB BOARD LAYOUT FOR ICS8431-11
ICS8431CM-11
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REV. A JULY 11, 2001
Integrated Circuit Systems, Inc.
ICS8431-11
255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - M SUFFIX
N
C
28
15
L E H
1
14
h x 45 D
A2
A
e B
A1
SEATING PLANE
.10 (.004)
TABLE 7. PACKAGE DIMENSIONS
SYMBOL MIN N A A1 A2 B C D E e H h L -0.10 2.05 0.33 0.18 17.70 7.40 2.65 -2.55 0.51 0.32 18.40 7.60 1.27 BASIC 10.00 0.25 0.40 0 10.65 0.75 1.27 8 Millimeters MAX 28 -0.0040 0.081 0.013 0.007 0.697 0.291 0.104 -0.100 0.020 0.013 0.724 0.299 MIN Inches MAX
0.050 BASIC 0.394 0.010 0.016 0 0.419 0.029 0.050 8
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MS-013, MO-119
ICS8431CM-11
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REV. A JULY 11, 2001
Integrated Circuit Systems, Inc.
ICS8431-11
255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER
Marking ICS8431CM-11 ICS8431CM-11 Package 28 Lead SOIC 28 Lead SOIC on Tape and Reel Count 26 Per Tube 1000 Temperature 0C to 70C 0C to 70C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS8431CM-11 ICS8431CM-11T
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. ICS8431CM-11
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